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NCV8665 150 mA Very Low Iq Low Dropout Linear Regulator with Reset and Delay Reset
The NCV8665 is a precision 5.0 V fixed output, low dropout integrated voltage regulator with an output current capability of 150 mA. Careful management of light load current consumption, combined with a low leakage process, achieve a typical quiescent ground current of 30 mA. NCV8665 is pin for pin compatible with the NCV8675 and the NCV4275 and it could replace this part when lower output current, and very low quiescent current is required. The output voltage is accurate within 2.0%, and maximum dropout voltage is 600 mV at full rated load current. It is internally protected against 45 V input transients, input supply reversal, output overcurrent faults, and excess die temperature. No external components are required to enable these features.
Features http://onsemi.com MARKING DIAGRAMS
1
5
D2PAK 5-PIN DS SUFFIX CASE 936A
V665-50G
AWLYWWG
1 8 V6655 ALYWX G
* * * * * *
* *
5 V Fixed Output (3.3 V and 2.5 V Versions are Also Available) 2.0% Output Accuracy, Over Full Temperature Range 40 mA Maximum Quiescent Current at IOUT = 100 mA 600 mV Maximum Dropout Voltage at 150 mA Load Current Wide Input Voltage Operating Range of 5.5 V to 45 V Internal Fault Protection -42 V Reverse Voltage Short Circuit Thermal Overload NCV Prefix for Automotive and Other Applications Requiring Site and Control Changes These are Pb-Free Devices
VIN Error Amplifier + - Current Limit and Saturation Sense VOUT
8 1
SOIC-8 D SUFFIX CASE 751
1 = Assembly Location = Wafer Lot = Year = Work Week = Lead Free Indicator
A WL, L Y WW, W G or G
PIN CONNECTIONS
D2PAK 1. VIN Pin 2. RO Tab, 3. GND* 4. D 5. VOUT * Tab is connected to Pin 3 Pin SOIC-8 1. VIN 2. RO 3. D 4. VOUT 5-8. GND
Bandgap Reference Thermal Shutdown D
ORDERING INFORMATION
Reset Generator
See detailed ordering and shipping information in the dimensions section on page 9 of this data sheet.
GND RO
Figure 1. Block Diagram
(c) Semiconductor Components Industries, LLC, 2008
September, 2008 - Rev. 1
1
Publication Order Number: NCV8665/D
NCV8665
PIN DESCRIPTIONS
Symbol VIN RO GND D VOUT Function Unregulated input voltage; 5.5 V to 45 V; Battery Input Voltage. Bypass to GND with a 0.1 mF ceramic capacitor. Reset Output; open collector active Reset (Accurate when VOUT > 1.0 V) Ground; Pin 3 internally connected to Tab Reset Delay; timing capacitor to GND for Reset Delay function Output; 2.0%, 150 mA. 10 mF, ESR < 16 W
ABSOLUTE MAXIMUM RATINGS
Pin Symbol, Parameter VIN, DC Input Voltage VOUT, DC Voltage Reset Output Voltage Reset Output Current Reset Delay Voltage Reset Delay Current Storage Temperature ESD Capability, Human body Model (Note 1) ESD Capability, Machine Model (Note 1) Moisture Sensitivity Level Symbol VIN VOUT VRO IRO VD ID TSTG VESDHB VESDMM MSL Min -42 -0.3 -0.3 -5.0 -0.3 -2.0 -55 4000 200 1 Max +45 +16 25 5.0 7.0 2.0 +150 Unit V V V mA V mA C V V -
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model (HBM) tested per AEC-Q100-002 (EIA/JESD22-A 114C) ESD Machine Model (MM) tested per AEC-Q100-003 (EIA/JESD22-A 115C) 2. Latchup Current Maximum Rating: 100 mA per JEDEC standard: JESD78.
OPERATING RANGE
Pin Symbol, Parameter Input Voltage Operating Range Junction Temperature Symbol VIN TJ Min 5.5 -40 Max 45 150 Unit V C
THERMAL RESISTANCE
Parameter Junction to Ambient (Note 3) Junction to Case (Note 3) Junction to Ambient (Note 4) Junction to Lead 6 (Note 4) 3. As 4. As to the leads. D2PAK D2PAK SOIC-8 SOIC-8 Symbol RqJA RqJC RqJA YqJL6 Min - - - - Max 85.4 6.8 138 21 traces directly connected C/W Unit
mounted on a 35x35x1mm FR4 PCB with a single layer of 100 mm2 of 1 oz copper heat spreading area. mounted on a 35x35x1mm FR4 PCB with a single layer of 100 mm2 of 1 oz copper heat spreading area including
Pb SOLDERING TEMPERATURE AND MSL
Parameter Lead Temperature Soldering Reflow (SMD styles only), Pb-Free (Note 5) MSL, 8-Lead EP, LS Temperature 260C 5. This device series incorporates ESD protection and exceeds the following ratings: Human Body Model (HBM) v 2.0 kV per JEDEC standard: JESD22-A114. Machine Model (MM) v 200 V per JEDEC standard: JESD22-A115. Symbol Tsld MSL Min - 1 Max 265 pk Unit C -
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NCV8665
ELECTRICAL CHARACTERISTICS VIN = 13.5 V, TJ = -40C to +150C, unless otherwise specified
Parameter OUTPUT Output Voltage Output Voltage VOUT VOUT 0.1 mA v IOUT v 150 mA (Note 6) 6 V v VIN v 28 V 0 mA v IOUT v 150 mA 5.5 V v VIN v 28 V -40_C v TJ v 125_C IOUT = 5 mA 8 V v VIN v 32 V 1 mA v IOUT v 150 mA (Note 6) IOUT = 100 mA (Notes 6 and 7) IOUT = 150 mA (Notes 6 and 7) IOUT = 100mA TJ = 25C TJ = -40C to +85C IOUT = 50 mA (Note 6) IOUT = 150 mA (Note 6) VRIPPLE = 0.5 VPP, F = 100 Hz IOUT = 0.1 mA to 150 mA 10 4.900 4.900 5.000 5.000 5.100 5.100 V V Symbol Test Conditions Min Typ Max Unit
Line Regulation Load Regulation Dropout Voltage Quiescent Current
DVOUT versus VIN DVOUT Vs. IOUT VIN - VOUT Iq
-25 -35
5 5 200 250 30 30 1.8 12 69
+25 +35 500 600 34 40 3.5 19
mV mV mV mA
Active Ground Current Power Supply Rejection Output Capacitor for Stability RESET TIMING D AND OUTPUT RO Reset Switching Threshold Reset Output Low Voltage Reset Output Leakage Current Reset Charging Current Upper Timing Threshold Reset Delay Time Reset Reaction Time PROTECTION Current Limit Short Circuit Current Limit Thermal shutdown threshold
IG(ON) PSRR COUT ESR
mA %/V
16
mF W
VOUT,rt VROL IROH ID,C VDU trd trr IOUT(LIM) IOUT(SC) TTSD
- RExt > 5.0 k, VOUT > 1.0 V VROH = 5.0 V VD = 1.0 V - CD = 47 nF CD = 47 nF VOUT = 4.5 V (Note 6) VOUT = 0 V (Note 6) (Note 8)
4.50 - - 2.0 1.2 10
4.65 0.20 0 4.0 1.3 16 1.5
4.80 0.40 10 6.5 1.4 22 4.0
V V mA mA V ms ms
150 100 150
500 500 200
mA mA C
6. Use pulse loading to limit power dissipation. 7. Dropout voltage = (VIN - VOUT), measured when the output voltage has dropped 100 mV relative to the nominal value obtained with VIN = 13.5 V. 8. Not tested in production. Limits are guaranteed by design.
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NCV8665
VIN CIN 100 nF IN 1 5 OUT IOUT COUT 10 mF ID CD 47 nF IRO VOUT
RRO 5.0 kW VRO
D 4 3 GND Iq 2
RO
Figure 2. Application Circuit
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NCV8665
TYPICAL CHARACTERISTIC CURVES
0.45 0.4 DROPOUT VOLTAGE (V) OUTPUT VOLTAGE (V) 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 0 50 100 LOAD CURRENT (mA) 150 200 125C 25C 6 5 4 3 2 1 Load = 5 mA 0 0 10 20 30 40 50 INPUT VOLTAGE (V)
-40C
Figure 3. NCV8665 Dropout Voltage vs. Load Current
6 5 4 ESR (W) 3 2 1 0 Load = 5 mA 0 2 4 6 8 10 18 16 14 12 10 8 6 4 2 0 0
Figure 4. NCV8665 Input Voltage vs. Output Voltage (Full Range)
Unstable Region
OUTPUT VOLTAGE (V)
Stable Region
Vin = 13.5 V CLOAD w 10 mF 50 100 150
INPUT VOLTAGE (V)
OUTPUT LOAD (mA)
Figure 5. NCV8665 Input Voltage vs. Output Voltage (Low Voltage)
10 9 QUIESCENT CURRENT (mA) 8 7 6 5 4 3 2 1 0 0 50 100 LOAD CURRENT (mA) 150 200 Vin = 13.5 V -40C QUIESCENT CURRENT (mA) 125C 25C 0.5 0.45 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 0
Figure 6. NCV8665 Stability Curve
125C 25C -40C
Vin = 13.5 V 5 10 15 20 25
LOAD CURRENT (mA)
Figure 7. NCV8665 Quiescent Current vs. Load Current (Full Range)
Figure 8. NCV8665 Quiescent Current vs. Load Current (Light Load)
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NCV8665
TYPICAL CHARACTERISTIC CURVES
0.05 QUIESCENT CURRENT (mA) QUIESCENT CURRENT (mA) 0.045 0.04 0.035 0.03 0.025 0.02 0.015 0.01 0.005 0 -50 0 50 TEMPERATURE (C) Vin = 13.5 V LOAD = 100 mA 100 150 10 9 8 7 6 5 4 3 2 1 0 0 10 20 30 40 50 LOAD = 50 mA
INPUT VOLTAGE
Figure 9. NCV8665 Quiescent Current vs. Temperature
Figure 10. NCV8665 Quiescent Current vs. Input Voltage
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NCV8665
Circuit Description
The NCV8665 is an integrated low dropout regulator that provides 5.0 V, 150 mA protected output and a signal for power on reset. The regulation is provided by a PNP pass transistor controlled by an error amplifier with a bandgap reference, which gives it the lowest possible drop out voltage and best possible temperature stability. The output current capability is 150 mA, and the base drive quiescent current is controlled to prevent over saturation when the input voltage is low or when the output is overloaded. The regulator is protected by both current limit and thermal shutdown. Thermal shutdown occurs above 150C to protect the IC during overloads and extreme ambient temperatures. The delay time for the reset output is adjustable by selection of the timing capacitor. See Figure 2, Application Circuit, for circuit element nomenclature illustration.
Regulator
Tantalum, aluminum electrolytic, film, or ceramic capacitors are all acceptable solutions, however attention must be paid to ESR constraints. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (-25C to -40C), both the capacitance and ESR of the capacitor will vary considerably. The capacitor manufacturer's data sheet usually provides this information. The value for the output capacitor COUT shown in Figure 2, Application Circuit, should work for most applications; however, it is not necessarily the optimized solution.
Reset Output
The error amplifier compares the reference voltage to a sample of the output voltage (VOUT) and drives the base of a PNP series pass transistor by a buffer. The reference is a bandgap design to give it a temperature-stable output. Saturation control of the PNP is a function of the load current and input voltage. Oversaturation of the output power device is prevented, and quiescent current in the ground pin is minimized.
Regulator Stability Considerations
The input capacitor (CIN) is necessary to stabilize the input impedance to avoid voltage line influences. The output capacitor helps determine three main characteristics of a linear regulator: startup delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints.
The reset output is used as the power on indicator to the microcontroller. This signal indicates when the output voltage is suitable for reliable operation of the controller. It pulls low when the output is not considered to be ready. RO is pulled up to VOUT by an external resistor, typically 5.0 kW in value. The input and output conditions that control the Reset Output and the relative timing are illustrated in Figure 11, Reset Timing. Output voltage regulation must be maintained for the delay time before the reset output signals a valid condition. The delay for the reset output is defined as the amount of time it takes the timing capacitor on the delay pin to charge from a residual voltage of 0 V to the upper timing threshold voltage VDU of 1.8 V. The charging current for this is ID of 5.5 mA. By using typical IC parameters with a 47 nF capacitor on the D Pin, the following time delay is derived: tRD = CD * VDU / ID tRD = 47 nF * (1.8 V) / 5.5 mA = 15.4 ms Other time delays can be obtained by changing the CD capacitor value.
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NCV8665
VI
t
VQ
< Reset Reaction Time VQ,rt t Reset Charge Current dVD + dt CD
VD
Upper Timing Threshold VDU Lower Timing Threshold VDL t Reset Delay Time Reset Reaction Time
VRO
t Power-on-Reset Thermal Shutdown Voltage Dip at Input Undervoltage Secondary Spike Overload at Output
Figure 11. Reset Timing Calculating Power Dissipation in a Single Output Linear Regulator
The maximum power dissipation for a single output regulator (Figure 12) is:
PD(max) + [VI(max) * VQ(min)] IQ(max) ) VI(max)Iq
(1)
In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required.
II VI SMART REGULATOR(R) IQ VQ
where is the maximum input VI(max) voltage, VQ(min) is the minimum output voltage, IQ(max) is the maximum output current for the application, Iq is the quiescent current the regulator consumes at IQ(max). Once the value of PD(max) is known, the maximum permissible value of RqJA can be calculated:
T RqJA + 150C * A PD
(2)
} Control Features
Iq
Figure 12. Single Output Regulator with Key Performance Parameters Labeled Heatsinks
The value of RqJA can then be compared with those in the package section of the data sheet. Those packages with RqJA's less than the calculated value in Equation NO TAG will keep the die temperature below 150C.
A heatsink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RqJA:
RqJA + RqJC ) RqCS ) RqSA
(3)
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NCV8665
where RqJC is the junction-to-case thermal resistance, RqCS is the case-to-heatsink thermal resistance, RqSA is the heatsink-to-ambient thermal resistance. RqJC appears in the package section of the data sheet. Like RqJA, it too is a function of package type. RqCS and RqSA are
THERMAL RESISTANCE JUNCTION-TO-AIR (C/W) 160 140 120 100 80 60 40 20 0 D2PAK 1 oz D2PAK 2 oz 100 200 300 400 500 600 700 800 900 COPPER AREA (mm2) 0.1 0.000001 0.0001 0.01 1 SOIC-8 1 oz R(t), (C/W) SOIC-8 2 oz 100 SOIC-8 D2PAK 10
functions of the package type, heatsink and the interface between them. These values appear in heatsink data sheets of heatsink manufacturers. Thermal, mounting, and heatsinking considerations are discussed in the ON Semiconductor application note AN1040/D.
1000
1 Single Pulse 100
PULSE TIME (sec)
Figure 13. Thermal Resistance vs. PCB Area
Figure 14. NCV8675 @ PCB Cu Area 100 mm2 PCB Cu thk 1 oz
ORDERING INFORMATION
Device NCV8665DS50G NCV8665DS50R4G NCV8665D50G NCV8665D50R2G Package D2PAK (Pb-Free) D2PAK (Pb-Free) SOIC-8 (Pb-Free) SOIC-8 (Pb-Free) Shipping 50 Units / Rail 800 / Tape & Reel 98 Units / Rail 2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
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NCV8665
PACKAGE DIMENSIONS
D2PAK, 5 LEAD DS SUFFIX CASE 936A-02 ISSUE C
-T- A K B
12345 OPTIONAL CHAMFER TERMINAL 6 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. TAB CONTOUR OPTIONAL WITHIN DIMENSIONS A AND K. 4. DIMENSIONS U AND V ESTABLISH A MINIMUM MOUNTING SURFACE FOR TERMINAL 6. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH OR GATE PROTRUSIONS. MOLD FLASH AND GATE PROTRUSIONS NOT TO EXCEED 0.025 (0.635) MAXIMUM. INCHES MIN MAX 0.386 0.403 0.356 0.368 0.170 0.180 0.026 0.036 0.045 0.055 0.067 BSC 0.539 0.579 0.050 REF 0.000 0.010 0.088 0.102 0.018 0.026 0.058 0.078 5 _ REF 0.116 REF 0.200 MIN 0.250 MIN MILLIMETERS MIN MAX 9.804 10.236 9.042 9.347 4.318 4.572 0.660 0.914 1.143 1.397 1.702 BSC 13.691 14.707 1.270 REF 0.000 0.254 2.235 2.591 0.457 0.660 1.473 1.981 5 _ REF 2.946 REF 5.080 MIN 6.350 MIN
E V
U
S H M L
D 0.010 (0.254)
M
T
N G R
P
C
SOLDERING FOOTPRINT*
8.38 0.33 1.702 0.067 10.66 0.42
DIM A B C D E G H K L M N P R S U V
16.02 0.63
3.05 0.12
1.016 0.04
SCALE 3:1
mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NCV8665
PACKAGE DIMENSIONS
SOIC-8 NB CASE 751-07 ISSUE AJ
-X-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
A
8 5
B
1
S
4
0.25 (0.010)
M
Y
M
-Y- G
K
C -Z- H D 0.25 (0.010)
M SEATING PLANE
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
SOLDERING FOOTPRINT*
1.52 0.060
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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NCV8665/D

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